Freelancer profile translated to English.
Back to original languageAbout Riad
Over my 25 years of experience, I have developed both hardware and software skills. I have designed dozens of projects on FPGAs (Xilinx and Altera) or microcontrollers (PIC, STM32, Raspberry Pi, and Arduino) in diverse fields such as image processing (segmentation, compression), DSP (FFT, filtering), telecommunications (modulation, turbo codes, hyper-codes encoding/decoding), or multimedia (USB, HMI). Furthermore, coming from academia, I am accustomed to presenting my work and writing technical, scientific, or educational documents.
Currently, I am working on extending the open-source RISC-V instruction set. I have already implemented several pipelined processor versions in VHDL, with which I have built some microcontrollers that I integrated onto FPGAs (Zybo and ZedBoard). As part of my research, I have also implemented my RISC-V processor cores down to the silicon level (layout), using Cadence CAD tools and TSMC 28nm silicon technology.
My knowledge of software development tools (Eclipse CDT, gcc, as, ld, ...) has enabled me to compile C programs on my own bare-metal targets and thus generate the necessary memory initialization files for simulation with Modelsim at the RTL level, and for prototyping on FPGA boards with Vivado. I have notably configured and compiled the CoreMark benchmark to measure the performance of my implementations.
Finally, I have successfully evaluated RISC-V standard compatibility. To do this, I compared the instruction trace of my processors and the content of my system's data memory with those generated by riscvOVPsim, the official reference simulator from RISC-V International, for a set of test programs.
French
Native or bilingual
English
Fluent
Remote only
Primarily works remotely
Experience
- Ecole Nationale d'Ingénieurs de TunisAssistant Professor in MicroelectronicsEDUCATION AND E-LEARNINGOctober 2004 - Today (21 years and 8 months)Tunis, TunisiaI teach digital system hardware design (VHDL, FPGA), communication in SoCs (AMBA AHB, APB, and AXI), RISC processor architecture (MIPS, RISC-V), hardware accelerator design (dataflow, pipeline), as well as microcontroller and embedded system programming (STM32, PIC, Arduino, Raspberry PI).My research activities focus on RISC-V processor architecture and associated development tools, runtime reconfigurable systems, and the hardware implementation of image processing or communication algorithms (FPGA or ASIC).I have also personally supervised numerous final year projects carried out by my students on these same topics, and overseen internships in industrial companies or R&D organizations (ST Microelectronics, Infineon, ARM, Synopsys, Mentor Graphics, Sagem, CEA, EADS, ...).
- ProsilogR&D EngineerTECHApril 2001 - September 2004 (3 years and 6 months)Cergy-Pontoise, FranceDevelopment of hardware IP blocks for SoC communication in VHDL (P2P, bus, NoC) with several protocols (AMBA AHB/APB, Altera Avalon, CoreConnect PLB/OPB, VCI, OCP, AMBA AXI), as well as SystemC models at different abstraction levels.Setup of demonstration platforms with SystemC and writing of a set of educational documents.
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Education
- PhD in Image and Signal ProcessingEcole Nationale de l'Electronique et des ses Applications (ENSEA)2000Titre : Conception d'une architecture matérielle reconfigurable dynamiquement dédiée au traitement d'images en temps réel Laboratoire Traitement de l'Information et des Systèmes ETIS ENSEA - Université de Cergy-Pontoise Afin de faire face aux besoins de puissance de calcul toujours croissants des algorithmes de traitement d'images, j'ai été chargé d'analyser deux chaînes de segmentation d'images et de proposer une architecture matérielle à base de FPGA, exploitant la reconfiguration dynamique. Cette technique, alors innovante, a permis de réduire la taille du système, tout en augmentant ses capacités d'évolution. En collaboration avec d'autres équipes de recherche (GDR ISIS et GDR AMN), j'ai pu concevoir le système modulaire ARDOISE, qui sera fabriqué en plusieurs dizaines d'exemplaires et utilisé par une douzaine de laboratoires de recherche.
- Master's Degree in Electronic Systems for Information Processing (SETI)Université Paris-Sud (Orsay Paris XI)1996Systèmes temps-réel Architectures numériques (processeurs, DSP, flot de données, pipeline, parallélisme, ...) Conception matérielles des systèmes embarqués (VHDL, FPGA, budget temps, budget énergie, ...) Microcontrôleurs (68HC11, 80C51, interfaces de communication parallèle/série et synchrone/asynchrone, ...) Modélisation et spécification des systèmes (approche objet : C++, UML, approche synchrone : Signal/Syndex, Lustre, Esterel, ...)