About Pablo
English
Native or bilingual
French
Conversational
Spanish
Native or bilingual
Experience
- Tecnun - Universidad de NavarraPhD StudentINTERNET OF THINGS (IOT)September 2022 - Today (3 years and 9 months)San Sebastian, PV, SpainI am a PhD student in the Applied Engineering PhD Program at Tecnun - University of Navarra. My thesis focuses on the design and implementation of a Chipless RFID system composed of an Ultra-WideBand reader with a specific antenna and sensors, wireless and chip-less for massive monitoring in IoT applications.Teaching collaboration in the following courses:
- Data Processing (Degrees in Telecommunication Systems Engineering and Artificial Intelligence Engineering)
- Mobile and Wireless Systems (Master's in Telecommunication Engineering)
Completed PhD courses:- Research in the University: Interdisciplinarity, Ethics, and Society
- Research Methodology
- Analog Signal Acquisition and Measurement
- Scientific Documentation and Communication
- Intellectual Property and Entrepreneurship
- Massachusetts Institute of TechnologyVisiting PhD StudentOctober 2024 - November 2024 (1 month)Cambridge, MA, USADuring my stay at MIT, I worked on the experimental validation of a wireless sensing system based on previously developed chipless RFID technology. My work focused on evaluating the reader's performance in real environments, analyzing aspects such as measurement stability, robustness against interference, and reproducibility of results. Additionally, I collaborated with the research team in interpreting the obtained data and identifying the system's limitations and potential improvements. This stay allowed me to contrast the technology's viability in an international context and reinforce its potential for practical applications.
- Fraunhofer IISResearch AssistantFebruary 2022 - July 2022 (5 months)Nuremberg, BY, GermanyDuring my Master's Final Project, I developed and implemented in VHDL an Adaptive Notch Filter – Adaptive Frequency Locked Loop (ANF-AFLL) system for mitigating chirp FMCW interference in GNSS receivers.
- Implemented in hardware (VHDL) the Python models of the FLL and LBCA, designing its complete architecture for execution on a Xilinx ZynqUltraScale+ FPGA.
- Developed the frequency discriminator, loop filter, NCO, and adaptive bandwidth control (LBCA) modules.
- Integrated the new modules with an adaptive notch filter, obtaining a real-time operational ANF-AFLL system on a Xilinx ZynqUltraScale+ FPGA.
- First hardware implementation of the LBCA algorithm developed at Fraunhofer IIS.
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Education
- Master's Degree2022Máster
- C1 Advanced New trends in Tech Transfer Actions.From lab to societyC1 Advanced New trends in Tech Transfer Actions.