About Oussama
Over 10 years in ASIC and FPGA design and verification. Very strong practical knowledge of VHDL/Verilog design flow including synthesis, timing analysis, logic simulation, functional/formal verification, emulation and prototyping.
French
Native or bilingual
English
Fluent
Can work on-site
Paris (up to 30km)
Experience
- Safran Electronics & DefenseFPGA EngineerMarch 2023 - December 2023 (9 months)Massy, FranceVHDL, FPGAs Xilinx, Time Sensitive Networks.
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Education
- Doctor of PhilosophyUniversité de Bretagne-Sud2014PhD, Study of non-binary LDPC decoders
- Master 2, Micro-technologies of communication systemsUniversité Paris-Est Marne-la-Vallée2010Master 2, Micro-technologies of communication systems