Freelancer profile translated to English.
Back to original languageAbout Abir
I have significant experience in the design, validation, and implementation of VHDL blocks on FPGA with a very small footprint.
The design of VHDL blocks is done at the level of basic elements (flip-flops, counters, memories..)
Arabic
Native or bilingual
French
Native or bilingual
English
Fluent
Can work on-site
Bry-sur-Marne (up to 50km)
Experience
- vitecFreelance Digital Design Engineer (VHDL, FPGA, ASIC, DO-254)TELECOMMUNICATIONSFebruary 2023 - Today (3 years and 3 months)Châtillon, FranceDesign of an IP to make a Move function of a memory at Byte level.RTL IP specification, simulation and validation.ASIC synthesis.Test and integration.Image processing test and validation.
- Safran Electronics & DefenseFreelance Digital Design Engineer (VHDL, FPGA, ASIC, DO-254)AVIATION AND AEROSPACEOctober 2022 - February 2023 (4 months)Paris, FranceOptimization of ALU Design in SystemVerilog.Adding Macro functions for matrix computation.Test and validation Design.
- Safe Connect SystemsHardware Team LeaderAVIATION AND AEROSPACEJuly 2017 - January 2022 (4 years and 6 months)• System specification of a deterministic Ethernet TSN network with a small footprint.• Drafting of specifications for blocks to be developed (timing, detailed specifications, FSM)• Specification, design, testing, and FPGA validation of the main IPs used for creating a deterministic Ethernet network (Rx, Tx, libraries, internal buses..)• Specification, design, testing, and validation of RGMII/SGMII interfaces (1Gbp, 100 Mbps)• Design and implementation of a TSN switch with 12 ports on ARRIA 10 (Intel Attila Board)• Establishment with the team of several architectures based on switches, EndPoints...• Development of a configuration tool with a graphical user interface on Python allowing the user to initialize their TSN switch.• Drafting of communication documents (CIR, marketing...)• Representation of the company at various trade shows and events: SPS2019 (Nuremberg), ERTS2 2020 (Toulouse)…Tools: Modelsim, Intel Quartus (17.1, 18.1), VHDL, Arria 10, Cyclone 10
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Education
- PHD MicroelectronicsENSTA Paristech2012Projet industriel MPSOCExplorer (ENSTA Paristech, Eve Company, Arteris) • Conception et implémentation d’une architecture à base de multiprocesseurs sur puces (Multi Processor System On Chip MPSOC) avec la technologie 3D IC de Tezzaron. Une comparaison entre différentes architectures : Butterfly et Mesh • Conception des réseaux sur puces avec la topologie Butterfly et Mesh. • Conception d’une architecture MPSOC avec 16 processeurs, 16 mémoires et un réseau sur puce NoC avec la topologie Butterfly. Emulation de cette architecture sur les plateformes Multi FPGA de EVE Company (Zebu UF4 et Zebu Server). • Conception et implémentation d’un MPSOC hiérarchique (64 processeurs et 64 mémoires)
- Microelectronics EngineerEcole Nationale des ingénieurs de Tunis2008