Freelancer profile translated to English.

Description

Engineer in electronic design and FPGA development, graduated with a specialized Master's degree in integrated electronic systems (University of Montpellier). I have acquired solid experience in demanding sectors such as medical (imaging, ultrasound), space, and nuclear.

Versatile, I master the entire product development cycle: from R&D to embedded software development on FPGA and hardware development.

Key Skills:

• FPGA (VHDL/Verilog – Xilinx, Lattice)

• PCB Design (Altium, OrCAD, KiCAD, CadStar)

• R&D Project Management

• Windows and Linux Environments

• Currently training: embedded programming in C/C++

Rigorous, curious, and motivated, I am driven by a passion for technical challenges and innovation.

Languages

Kabyle
Native or bilingual
French
Native or bilingual
English
Fluent
Arabic
Native or bilingual

Workplace preferences

Can work on-site

Montpellier (up to 50km)

Invis'art technology
FPGA & Electronics Engineer
HEALTH AND WELLNESS
January 2023 - August 2024 (1 year and 8 months)
Narbonne, France
-FPGA developments in the medical environment
-Developments on a Lattice target
- Signal processing
-MIPI camera control
-Development of the VHDL FPGA firmware architecture
o Implementation of image reconstruction systems captured by cameras.
o SPI Flash Memory Controller
o Serdes link
o DDR3
o IMU (9-axis)
o Temperature sensor.
o MIPI protocol
o UART, I2C, fast UART, Serdes communication
o Motion estimator
o Kalman and complementary filter
o RGB
o LVDS
o Video streaming and image capture
VHDL Information Verification Documentation Nuclear
ElsysDesign
FPGA Development Engineer
RAW MATERIALS INDUSTRY
March 2022 - January 2023 (10 months)
Aix-en-Provence, France

- Development of the Zynq XILINX FPGA firmware architecture in Verilog and VHDL
o Tests and updates of simulation files for the new FPGA board in VHDL and VERILOG.
o Implementation and construction of Embedded LINUX on ZYNQ.
o Study of the camera sensor's bushbroom operation.
o Python Scripts
o LVDS link in SDR format.
o UARTlite control register
o Implementation of an IP for receiving LVDS data in SDR format on Zynq FPGA, respecting AXI and AXIS protocols.

• Translation of old systems into VHDL and Verilog
o Translation of schematic systems to VHDL 95 and 2008
o Debugging of old products dedicated to a NAI source
o Python scripts for simulation
o G96 protocol

- Documentation in V-cycle.
o Use of high-performance software to automate documentation, on Sigasi and PyCharm.
o Customer support based in England on various source codes and documents.

• Radioactivity training (nuclear without certification)
FPGA VHDL Xilinx Embedded Systems Documentation
Loft Orbital
Firmware Engineer
AVIATION AND AEROSPACE
May 2021 - March 2022 (9 months)
Toulouse, France
• Development of the Zynq XILINX FPGA firmware architecture in Verilog and VHDL
o Tests and updates of simulation files for the new FPGA board in VHDL and VERILOG.
o Implementation and construction of Embedded LINUX on ZYNQ.
o Testing of a hyperspectral camera in Orbit
o Study of the camera sensor's bushbroom operation.
o Python Scripts
o LVDS link in SDR format.
o UARTlite control register
o Implementation of an IP for receiving LVDS data in SDR format on Zynq FPGA, respecting AXI and AXIS protocols.

• Radio Frequency (filtering and IQ acquisition under FPGA, hardware front-end design)
o Design of an IP to increase bandwidth, offering the choice for the RX channel part to be two channels or a single channel after FIR filtering for RF signal IQ acquisitions
o Sampling frequency 896ksps (1708.9MB) with 350kHz BW

• Development of a SpaceWire router IP.
o SpaceWire standard ECSS-E-ST-50-12C
o Existing packet formats as mentioned in the ECSS-E-ST-50-12C standard.
o Development of the router in VHDL.
o Perform the same procedure as implemented in software.
o Preliminary studies on Microsemi FPGA (PolarFIRE) for the future YAM5 mission.
o Work under the GitLab and Atlassian environment.
o Training work on SDR Pluto (an FPGA connected to an Analog Devices ADC) to understand Radio Frequency signals.
o Research and studies on REED SOLOMON and ECC Algorithms.
o Contact with clients.
FPGA VHDL Python (Programming Language) SpaceWire C/C++