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Nicolas CastelNC

Nicolas Castel

Design & Verif FPGA/ASIC | VHDL & VERILOG

€550/day
Aix-en-Provence, FR
3-7 years

Average response time: 1 hour

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About Nicolas

Graduate of the Master's degree in electronic systems and computer systems from Sorbonne Université.

I am a digital design engineer with 6 years of experience specializing in RTL design, verification, and synthesis for ASIC and FPGA.
  • French

    Native or bilingual

  • English

    Fluent

Can work on-site
Aix-en-Provence (up to 50km), Nice (up to 50km)

Experience

  • Theryq (Next generation Radiotherapy Flash),
    FPGA RTL Design Engineer | October 2024 to April 2026 (1.5 years)
    MEDICAL
    October 2024 - April 2026 (1 year and 6 months)
    Peynier, France
    - Design and verification of high-precision real-time RTL architectures for a medical device, achieving timing closure on resource-constrained Microchip FPGA platforms
    FPGA VHDL Signal Processing Real-time Regression Testing
  • Idemia Secure Transaction,
    ASIC RTL Design Engineer | September 2023 to August 2024 (1 year)
    BANKING AND INSURANCE
    September 2023 - August 2024 (11 months)
    Meyreuil, France
    - Select and integrate a RISC-V CPU to replace the licensed CPU used in Idemia's designs. RTL verification of several Verilog architectures for secure products.
    Verilog RISC-V Cadence ASIC Regression Testing
  • Faurecia Clarion Electronics,
    ASIC RTL Design Engineer | June 2020 to June 2023 (3 years)
    AUTOMOBILE
    June 2020 - June 2023 (3 years)
    Paris, France
    - ASIC development for radio and TV reception in cars. Development of the audio IPs and an architecture including an opencore CPU.
    ASIC Cadence VHDL Static Synthesis Regression Testing

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Education

  • Master in Microelectronics
    Sorbonne Université
    2019
    Development fpga Traitement du signal Électronique analogique Programmation bas niveau
  • Bachelor in Electronics
    Université Pierre et Marie Curie
    2017

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