Clément La Batie

Clément LA BÂTIE, 33-year-old embedded systems engineer, based in Lorient, a graduate of ESIEE Paris in embedded systems. With 9 years of experience, including 6 at Safran Electronics & Defense, I have specialized in the design, verification, and optimization of FPGAs.

I have also led operational committees (COMOP/COPIL), projects, managed continuous improvement and cybersecurity progress plans, and developed test FPGAs to validate boards and interfaces. I have expertise in failures and obsolescence while creating reusable VHDL libraries. I have also worked in Verilog, C++, and Python.

Key skills: Project management, ASIC/FPGA verification, debugging, rail/aeronautical standards, cybersecurity.

Digital Electronics and Programmable Logic

FPGA –VHDL –verilog

Foundries, software, and targets encountered:

• Xilinx: Software: Xilinx ISE– Vivado– ILA– SDK

Main targets: 7 series: artix 7– zynq 7000– zynq ultrascale

• Altera/Intel: Software: Quartus prime– Signal TAP– Nios II

Main targets: Cyclone V– Cyclone 10– MAX10– Arria10

• Microsemi: Software: libero

Main targets: IGLOO2 – smartfusion

• Lattice: Software: iCEcube2 – Diamond

Main target: MACHXO3

Environment:

• Interfaces encountered: SPI – QSPI – UART – RS232 – RS422 – GPIO –I2C –PCIe–Ethernet

• Mainly interfaced components: STM32 – FLASH – RAM

EEPROM –DAC –ADC (gyroscope – ultrasonic sensor – temperature probe) – SoC– FPGA – CPLD

• Analog electronics: basic – analysis of board schematics

• Computer languages: C – C++ –Python – TTL

• Methods: Agile Methods – V-Cycle – Product Lifecycle Management (PLM) – GIT – SVN – Failure Expertise – Project Management

• Tools: Microsoft Office – Microsoft 365 – notepad++ – gitkraken - MyPLM–vpn–anydesk– teamviewer– bomgar– version one - 3DExperience – SAP