Christoph Fauck

In video walls, video data is streamed via a video controller that buffers a video data stream from standard interfaces like HDMI or DisplayPort into a frame buffer and streams it from there via Ethernet into the video wall.

For such a high-throughput video controller, I:

A Qt application, running on the embedded Linux with LXDE interface, connects to the CLI program via a library.

The hardware of the video controller is a carrier board with 12 SFP+ slots (4x10G Ethernet**, 8x **1G Ethernet**), one DisplayPort input, and two **DisplayPortoutputs, an SoM with anArria10 SoCwith two separate DDR4 memory banks (HPS and FPGA) to maximize bandwidth.

Via a DisplayPort input, video data is streamed into theDDR4memory, designed as a double buffer. The data is read out according to the size and layout of the video panels in the video image, packed into **UDP packets**, and sent via Ethernet to the video wall. The video controller supports resolutions up to 16k with color depths up to 12 bits.

The system uses fiber optic cables for precise temperature measurement over long distances by evaluating Stokes and anti-Stokes reflections in the optical fiber. The control of the laser pulses as well as the high-frequency acquisition and preprocessing of the measurement data were realized on specific customer hardware, with the data being transferred via PCIe to a system processor for final temperature determination.

I have completely planned and implemented the FPGA design. Laser control was done via a BRAM table writable via PCIe. To enable precise phase shifting of the laser, a circuit part with a timing requirement of 1 GHz was necessary.

The measurement data was acquired in a DDR3 memory connected via a Memory Interface Generator (MIG). To minimize systematic memory noise, I implemented a memory shifting logic with averaging. The final measurement data was finally provided via the PCIe interface for evaluation, via which the logic was also configured and controlled.

Development of the complete electronics and hardware-near software infrastructure for an industrial printing system.

The architecture uses the heterogeneous computing power of an i.MX8M Mini (Cortex-A53 and Cortex-M4) to separate the web interface, print rendering, and real-time print control.

I developed the entire electronics of the printer. A mainboard with an i.MX8MM SoM, which was expanded with power sequencing, a second Ethernet (PCIe-to-Ethernet bridge and a PoE controller including 48V generation from 24V), an FPGA for controlling the motor controller and print head, an STM32, and a motor driver for commutating two BLDC motors for winding, as well as numerous I/O interfaces. The electronics had to meet surge resistance requirements. I personally assembled and soldered the first prototypes in my own reflow oven.

I completely planned and implemented the FPGA design, as well as the motor controls on the STM32 microcontroller (sinusoidal and block commutation).

A Yocto-based embedded Linux from Variscite runs on the i.MX8 (Cortex A53 cores), which I customized. A bare-metal real-time control developed by me runs on the Cortex M4 core, which controls the FPGA and the STM32. The CM4 subsystem is integrated into the Linux system via a Linux driver (RPMSG) written by me.

A C# based software runs in the Linux userspace for rendering labels, pre-calculating print control data, and a web interface for configuration from another supplier, which I integrated into the system via Yocto. The project was shared with the supplier.