Freelancer profile translated to English.

Description

FPGA and embedded SoC engineer, expert in VHDL development, functional verification, and on-target validation. Specializing in Hardware/Software architectures, for complex industrial PC systems with PCIe/DMA communication as well as advanced designs integrating Xilinx Zynq-7000 SoCs (ARM + programmable logic integration).

I support my clients throughout the entire development cycle: architecture definition, implementation, verification, timing optimization, and resolution of critical issues (CDC, latency, system robustness).

Languages

French
Native or bilingual
English
Native or bilingual

Workplace preferences

Can work on-site

Strasbourg (up to 50km), Paris (up to 15km), Lyon (up to 10km), Grenoble (up to 10km)

ADDI-DATA GmbH,
Firmware Engineer
July 2023 - Today (2 years and 11 months)
Baden, BW, Germany
Propose Hardware/Software communication architecture (PCIe/PCI Communication)
Integration and implementation of hard IP (PCIe),
Implementation of DMA Controller, interrupt management (MSI/Line based).
Interfacing the FPGA with different chips (Flash memory, FPGA slave),
Mastery of FPGA Configuration (AS & PS configuration)
Implementation of FPGA verification & validation plan according to specifications Development and virtual VHDL verification (Quartus + Modelsim) + Debugging on physical board. (Timing constraint analysis and resolution)
Development of low-level C driver for interfacing with PCIe peripherals.
Client project
GIT/SVN Management
FPGA VHDL Quartus Embedded Systems PCIE
MBDA
FPGA Design Verification
DEFENSE AND MILITARY
July 2022 - July 2023 (1 year)
Le Plessis-Robinson, France
•Analysis and understanding of client requirements.
•Development of a verification and validation plan.
•Creation of different test scenarios stimulating the design inputs/outputs.
•Development of a virtual testbench under ModelSim (UVM Methodology).
•Implementation of scripts for running regression tests and automatic error detection.
. Verification with 100% code coverage rate
•Writing a verification document tracing the tests performed and attesting to the compliance of verifiable requirements.
Modelsim UVM Verification Automated Test Bench
MBDA,
FPGA Design and Verification
July 2021 - July 2022 (1 year)
Bourges, France
•In-depth analysis and complete understanding of the security protocol specification.
•Technical exchanges with the client to clarify and correct certain requirements deemed irrelevant or inconsistent with the IEC standard.
•Development of an architecture meeting functional and safety requirements.
•VHDL design, analysis and justification of warnings generated during synthesis and Place & Route.
•Writing a design document detailing the chosen architectural choices as well as a complete description of each design module.