Freelancer profile translated to English.

Description

FPGA specialist focused on industrial prototyping and hardware validation.

I support industrial teams and deep-tech startups in transforming RTL designs into robust FPGA prototypes ready for demanding technical environments.

My expertise covers:

• FPGA Integration (Xilinx / Vivado)

• RTL Development (VHDL / Verilog / SystemVerilog)

• Digital PCB Design and Schematic Capture

• Power Supply Design and Board Bring-up

• Hardware Validation and Signal Analysis

I am involved from architecture definition and RTL development through to FPGA deployment, PCB integration, and complete system validation.

Experience in complex digital systems integration and validation in an industrial environment.

Available for short industrial missions (1–3 months), prototype development, and technical support on complex projects.

Languages

Workplace preferences

Can work on-site

Grenoble (up to 50km)

NovaiCore
FPGA & Hardware Validation Engineer
November 2024 - June 2025 (7 months)
Grenoble, France
Designed an FPGA-based industrial leveling controller for real-time monitoring and actuation.
Integrated RS-232 communication, user inputs, relay outputs, and status interfaces.
Contributed to PCB design and board-level hardware integration.
Supported hardware validation of sensing, control, and output stages.
Delivered an embedded control platform combining FPGA logic and custom hardware interfacing.
FPGA PCB design VHDL Embedded Systems Hardware Validation
NovaiCore
FPGA & Mixed-Signal Engineer
September 2023 - December 2023 (3 months)
Grenoble, France
Implemented a high-speed FPGA interface for ADC/DAC signal-chain bring-up, including converter control, digital data-path integration, timing validation, and real-hardware testing. The project focused on reliable FPGA interfacing with high-speed mixed-signal devices in a performance-oriented hardware platform.
FPGA Mixed-Signal ADC/DAC Hardware Validation Timing Validation
NovaiCore
FPGA Co-Design Engineer
March 2023 - August 2023 (5 months)
Developed an FPGA-based scene matching accelerator using a sliding-window template matching approach with SAD computation. The architecture combined dedicated hardware acceleration for intensive matching operations with on-chip memory management and control logic for efficient image-processing workflows.
FPGA RTL Image Processing Digital Design Co-Design

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